1. Technical Field of the Invention
The present invention relates to a method of testing dynamic random access memory (DRAM), and particularly to a method for more rapidly testing the storage capability of memory cells in DRAM devices.
2. Background of the Invention
There are two known types of semiconductor memory, one referred as volatile memory and the other referred as non-volatile memory. In volatile memories the stored data is lost when the power supply is removed from the semiconductor device. A non-volatile memory, on the other hand, retains the data stored for extended periods after the power supply to the device has been removed. In a computer or related systems, non-volatile memory is used for long-term storage of programs and data which seldom or never change, and volatile memory devices are used for the short-term storage of program instructions and data during the execution of a program.
Volatile memory devices may be divided into two categories. Static Random Access Memory (SRAM) consists of flip-flop latches such that each SRAM latch maintains a bit of data so long as power is provided to the SRAM. In dynamic memories, a charge representing a data bit is stored on a capacitor.
Conventional DRAM cells employ a single transistor architecture wherein the memory cell comprises a storage capacitor having a first terminal connected to a reference voltage, such as Vss, and a second terminal connected to a pass and/or transmission gate transistor. The pass gate transistor serves to transport charge to the storage capacitor, and also to read the charged or uncharged state of the storage capacitor. The gate electrode of the pass/transmission gate transistor is tied to a word line decode signal and the drain electrode thereof is connected to a bit line. Data is stored in the memory cell as a charge on the storage capacitor. However, because data is stored in a dynamic memory cell as a charge on a capacitor and because memory cells experience leakage current either from the storage capacitor or the pass gate transistor, the stored charge in a dynamic memory cell, particularly a stored charge representing a high logic level, decays over time. Each bit of data in a DRAM device must therefore be periodically refreshed before it has irretrievably decayed.
The pass gate transistor of a dynamic memory cell typically comprises an N-channel field effect transistor. When attempting to store a high logic level (Vdd) into a dynamic memory cell by providing a Vdd level signal to the selected word line and gate electrode of the memory cell pass gate transistor connected thereto, the maximum charge which can be stored on the storage capacitor is Vdd-Vtn, wherein Vtn is the threshold voltage of the pass gate transistor taking into account back bias thereof. Combined with the fact that the charge stored on memory cell storage capacitors decays over time, this maximum voltage level limit necessitates the dynamic memory cells being refreshed relatively frequently.
Techniques have been previously undertaken to decrease the frequency of dynamic memory cell refresh operations. Such techniques include storing a greater charge on the memory cell capacitor during a write operation. One known technique for storing a greater charge on a dynamic memory cell capacitor includes boosting the voltage of the selected word line to a voltage greater than the high reference voltage level (Vdd) when performing a memory cell write operation, which thereby imposes a higher gate voltage on the pass gate transistor of the selected memory cell. Various bootstrapping circuits have been previously employed to increase word line voltage during a write operation. Through utilization of boostrapping circuits, it is possible to store a full high reference voltage level charge onto a dynamic memory cell capacitor so as to lower the frequency of the dynamic memory refresh operation.
Sense amplifiers are typically connected to the bit lines of dynamic memory to sense the small change in potential appearing on the bit lines following a memory cell read operation and to drive the bit lines to the appropriate full reference voltage level, such as Vdd or Vss. Once the sense amplifier drives the bit line to the full reference voltage level, the memory cell from which data was read is refreshed with the full reference voltage signal appearing on the bit line.
It is customary to test both the functionality and timing of integrated circuits in order to ensure that the final product performs as specified. With respect to dynamic memory, it is common to test the ability of dynamic memory cells to maintain a stored charge in order to screen dynamic memory devices having storage capacitors which sufficiently maintain a stored charge from dynamic memory devices having "weak" cells which fail to sufficiently maintain a stored charge. Because each memory cell of a dynamic memory must be tested to determine the ability of the dynamic memory to maintain stored data and hence function properly, it is important that test programs for integrated circuits employing dynamic memory and related systems thoroughly and efficiently test and/or characterize the dynamic memory.